duty cycle correction Duty

A 0.1–3.5-Ghz Duty-Cycle Measurement and Correction Technique in 130-Nm CMOS - YouTube

Duty Cycle Correction Factor

 · PDF 檔案Duty Cycle Correction Factor Test Method In order to try to obtain better measurements and comply with all the Rules of the Federal Communications Commission Part 15, Lucent Technologies Consumer Products L.P. test team, decided to test FHSS cordless
Patent Report: | US10158353 | Duty cycle correction method
A 50% duty‐cycle correction circuit for PLL output
We proposed a circuit for correcting the fluctuations in the duty cycle caused by the increase in the device fluctuations due to the miniaturization of MOS devices and faster operating speeds. This correction circuit uses feedback control consisting of duty‐cycle detection and correction to correct the fluctuations in the duty cycle of a phase‐locked loop (PLL) circuit produced during the
(a) Duty cycle correction (DCC) circuits for the Controller and (b)... | Download Scientific Diagram

Analogue feedback inverter based duty-cycle correction …

Duty cycle correction using negative feedback loop–An analog solution. In Proceedings of 16th international conference on mixed design of integrated circuits and systems (MIXDES 2009), Lodz, Poland. Google Scholar Mehta, R., Seth, S., Shashidharan, S A
Figure 6 from All digital duty-cycle correction circuit design and its applications in high-performance DRAM | Semantic Scholar
Clock buffer with duty cycle corrector
 · If duty cycle distortion occurs, steps are taken to insure that the distortion of the clocking circuit is minimal and the duty cycle is either preserved or corrected. The duty cycle of the clock can be either 50% or non-50% dependent on the applications.
Ευρεσιτεχνίες US20070290730 - Duty cycle correction circuit - Ευρεσιτεχνίες Google

A fast-locking all-digital deskew buffer with duty …

In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock
Duty Cycle correction circuit structure | Download Scientific Diagram

A Duty-Cycle Correction Circuit for High-Frequency Clocks

We present a circuit to control duty-cycle of high-frequency clocks with very fine resolution. The proposed duty-cycle detection and correction circuits are digital and do not require external references and matching devices. The circuits are designed to compensate for duty-cycle uncertainties in a floating point unit implemented using limited switch dynamic logic (LSDL) (Belloumini, 2005
Figure 2 from All digital duty-cycle correction circuit design and its applications in high-performance DRAM | Semantic Scholar

Power Factor Correction: What is it? (Formula, Circuit & …

By proper selection of duty cycle, we can get the desired shape of the current to the load. How to Size Power Factor Correction? To size the power factor correction, we need to calculate the requirement of reactive power (KVAR).
Patent US6643790 - Duty cycle correction circuit with frequency-dependent bias generator - Google Patents

A Duty Cycle Corrector (DCC) using a sigma-delta Analog …

In order to achieve fast duty-correction with a small area, sigma-delta ADC controller used as a duty cycle correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.12-μm CMOS technology. Duty-cycle correctors (DCCs) are
Patent US6535040 - Duty cycle correction circuits that reduce distortion caused by mismatched ... - Google Patents

DLPC34xx Controller Image Calibration

 · PDF 檔案example of duty cycle range is red from 10% to 50%, green from 20% to 60%, and blue from 10% www.ti.com How to Perform Factory White Point Correction using LED Duty …
Patent US6426660 - Duty-cycle correction circuit - Google Patents

Electronic Warfare and Radar Systems Engineering …

To express the duty cycle of equation [4] as a percentage, multiply the value obtained by 100 and add the percent symbol. Thus a duty cycle of 0.001 is also 0.1%. The duty cycle can be expressed logarithmically (dB) so it can be added to or subtracted from power measured in dBm/dBW rather than converting to, and using absolute units.
Patent US20110126162 - Design Structure for a Duty Cycle Correction Circuit - Google Patentsuche

An all‐digital DLL with duty‐cycle correction using …

Summary This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL
Patent US7202722 - Duty-cycle correction circuit - Google Patents

RE: Duty Cycle Correction facto

 · PDF 檔案Subject: Duty Cycle Correction factor for 15.231 device Dear FCC, Applicant has a keyless car entry sytem operating at 315 MHz. The system is deviced into two parts – manually activated transceiver (key itself) – activated transceiver (controller inside vehicle
Patent US6542015 - Duty cycle correction circuit and apparatus and method employing same - Google Patents
Clock buffer with duty cycle corrector
A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as i…
Analogue feedback inverter based duty-cycle correction | SpringerLink

IET Digital Library: CMOS digital duty cycle correction …

 · A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations.
Patent US6690218 - Method of performing duty cycle correction - Google Patents

An all-digital duty-cycle and phase-skew correction circuit for …

 · PDF 檔案The duty-cycle correction end signals CORR_DONE[1:0] select the detector input with two MUXs, an edge combiner of one AND gate and two /2 dividers. During the phase-skew correction, the blue lined signals CKpc and CKout 90 are used as input Fig. 1